Tracing is a technique for collecting trace information which is recorded on operation of a CPU, a hard macro, a bus and the like on a target chip, and can be read from the outside. In general, the trace information may faithfully express internal state of a component on the chip and thus is widely used for debugging, problem analysis, and various evaluations.
As a processing method using tracing, there has been known a non-invasive debugging method using an embedded tracing.
According to the non-invasive debugging method using the embedded tracing, operating information is collected in units of cycles from each target component operating at high speeds and then transferred through a dedicated route of a backplane to the outside of the target chip. Subsequently, the externally transferred trace information is analyzed by a dedicated viewer installed in a platform for development work, a personal computer, and the like.
To perform the embedded tracing, hardware needs for assist. Namely, hardware is required as a part of embodiment for embedded tracing. During performing the embedded tracing, operation of the target chip does not need to stop. Thus, the embedded tracing can acquire extremely reliable information, but needs to a mechanism for transferring a large amount of predefined recorded information to the outside.
Meantime, JTAG (Joint Test Action Group) has been known as an invasive debugging method. According to the JTAG method, a built-in function such as a break point and a watch point configured on a target chip is used to stop a CPU and a hard macro on the target chip, then debugging of the CPU or the hard macro is to be performed using referring and changing a register and a memory thereof and performing a step execution. Since such invasive debugging method may involve tweaking and stopping the target operation, the method may provide information about an operation different from the actual operation. Further, the method provides only pinpoint information and thus may lack in completeness of tracing information. On the other hand, the method may reduce burden in implementation and thin transmission lines suffices in many cases.
As another tracing method, there has been known a method using a bus tracing apparatus in multi-processor system, whereby a timer scale value and common bus trace information are stored in association with each other, then a time when the trace information occurs is determined and a trace sequence corresponding to a plurality of cores is captured.
As patent document, Japanese Patent Laid-Open No. 3-127253 may disclose an art related to the invention.
Conventionally, in order to externally transfer a large amount of predefined information in units of cycles, the non-invasive debugging method using embedded tracing needs not only a mechanism for externally transferring the trace information read from each component, but also a large volume intermediate buffer for storing a huge amount of the read data with a flow rate thereof, an interface with a high throughput and the like on the chip. Further, outside the chip, there is also required an interface and a large volume buffer for receiving the transferred trace information. Consequently, the conventional non-invasive debugging method using embedded tracing has a problem that there is a need to cope with a large physical capacity as a whole.
Therefore, there may be a problem in the conventional embedded tracing that a target chip is limited based on an estimated flow rate of trace information. For example, in a case that a trace target is a processor, trace information thereof may be generally an execution history data of the processor in units of instructions. Thus, when the processor is complicated in configuration and operates at high speeds, the embedded tracing needs a large scaled mechanism. Alternatively, in a case that a trace target is a hard macro, a trace information in a single tracing may involve a huge amount of data depending on configuration of the target hard macro. Further, in a case that a plurality of state machines exists in the target hard macro, the data of each state data multiplied by the number of state machines may need to be processed. Thus, in accordance with configuration of a target, the embedded tracing is required to devote a larger physical capacity to a mechanism for tracing.
As described above, conventionally, a target that is capable of installing the embedded tracing mechanism is limited to a relatively small component such as a prototype chip and an emulator chip. Moreover, it may be very difficult to implement the embedded tracing mechanism depending on constraint of chip configuration.
In light of the above-mentioned advantages of the embedded tracing, it is desirable to realize collection of trace information by installing and using an embedded tracing mechanism built-in a final chip form, namely, an actual product form.
However, it is more and more difficult to apply the embedded tracing mechanism built-in a chip due to physical restrictions because further integration of circuits and an increase in data processing amount for each component, and the like.